--Archivo: multiplicador_encauzado.vhd
--Fecha de creación: 15/01/2011
--Última fecha de modificación: 04/02/2011
--Diseñador: Pedro Marquez.
--Diseño: multiplicador_encauzado
--Propósito: Multiplicador encauzado de 4 etapas para un procesador vectorial
--			 Tiene 2 entradas de 4 bits cada una, las cuales se truncan a 2 bits

library IEEE;
use IEEE.std_logic_1164.all;

ENTITY multiplicador_encauzado IS
PORT (
 	X_i   : in  STD_LOGIC_VECTOR (3 downto 0);
    Y_i   : in  STD_LOGIC_VECTOR (3 downto 0);
	CLK   : in  STD_LOGIC;
    Z_o   : out  STD_LOGIC_VECTOR (3 downto 0) );
END multiplicador_encauzado;

ARCHITECTURE structural OF multiplicador_encauzado IS

	COMPONENT celda_multiplicadora
	PORT (	Multiplicando : IN std_logic;
		Multiplicador : IN std_logic;
		PP_IN : IN std_logic;
		C_IN : IN std_logic;
		C_OUT : OUT std_logic;
		PP_OUT : OUT std_logic );
	END COMPONENT;

	COMPONENT pipem
	PORT (	A_in  : in STD_LOGIC;
		B_in  : in STD_LOGIC;
		C_in  : in STD_LOGIC;
		D_in  : in STD_LOGIC;
		E_in  : in STD_LOGIC;
		F_in  : in STD_LOGIC;
 		CLK   : in STD_LOGIC;
		A_out : out STD_LOGIC;
		B_out : out STD_LOGIC;
		C_out : out STD_LOGIC;
		D_out : out STD_LOGIC;
		E_out : out STD_LOGIC;
		F_out : out STD_LOGIC );
	END COMPONENT;
	
signal Z0_signal1 : STD_LOGIC;
signal Z0_signal2 : STD_LOGIC;
signal Z0_signal3 : STD_LOGIC;
signal Z0_signal4 : STD_LOGIC;
signal Z0_signal5 : STD_LOGIC;

signal Z1_signal3 : STD_LOGIC;
signal Z1_signal4 : STD_LOGIC;
signal Z1_signal5 : STD_LOGIC;

signal Z2_signal4 : STD_LOGIC;
signal Z2_signal5 : STD_LOGIC;

signal Z3_signal4 : STD_LOGIC;
signal Z3_signal5 : STD_LOGIC;

signal C0_signal1 : STD_LOGIC;
signal C0_signal2 : STD_LOGIC;

signal C2_signal3 : STD_LOGIC;
signal C2_signal4 : STD_LOGIC;

signal P1_signal2 : STD_LOGIC;
signal P1_signal3 : STD_LOGIC;

signal C1_signal2 : STD_LOGIC;
signal C1_signal3 : STD_LOGIC;
signal C1_signal4 : STD_LOGIC;

signal X0_signal1 : STD_LOGIC;
signal X0_signal2 : STD_LOGIC;
signal X0_signal3 : STD_LOGIC;

signal Y0_signal1 : STD_LOGIC;
signal Y0_signal2 : STD_LOGIC;

signal X1_signal1 : STD_LOGIC;
signal X1_signal2 : STD_LOGIC;
signal X1_signal3 : STD_LOGIC;
signal X1_signal4 : STD_LOGIC;

signal Y1_signal1 : STD_LOGIC;
signal Y1_signal2 : STD_LOGIC;
signal Y1_signal3 : STD_LOGIC;
signal Y1_signal4 : STD_LOGIC;

signal E_signal4 : STD_LOGIC;
signal F_signal4 : STD_LOGIC;
signal E_signal5 : STD_LOGIC;
signal F_signal5 : STD_LOGIC;

begin

	mult1 : celda_multiplicadora PORT MAP( 	
			Multiplicando => X_i(0),
			Multiplicador => Y_i(0),
			PP_IN => '0',
			C_IN => '0',
			C_OUT => C0_signal1,
			PP_OUT => Z0_signal1);

	X0_signal1 <= X_i(0);
	X1_signal1 <= X_i(1);
	Y0_signal1 <= Y_i(0);
	Y1_signal1 <= Y_i(1);

	pipe1 : pipem PORT MAP(
			A_in => Z0_signal1,
			B_in => C0_signal1,
			C_in => X0_signal1,
			D_in => X1_signal1,
			E_in => Y0_signal1,
			F_in => Y1_signal1,
 			CLK  => CLK,
			A_out => Z0_signal2,
			B_out => C0_signal2,
			C_out => X0_signal2,
			D_out => X1_signal2,
			E_out => Y0_signal2,
			F_out => Y1_signal2 );

	mult2 : celda_multiplicadora PORT MAP( 	
			Multiplicando => X1_signal2,
			Multiplicador => Y0_signal2,
			PP_IN => '0',
			C_IN => C0_signal2,
			C_OUT => C1_signal2,
			PP_OUT => P1_signal2);

	pipe2 : pipem PORT MAP(
			A_in => Z0_signal2,
			B_in => P1_signal2,
			C_in => C1_signal2,
			D_in => X0_signal2,
			E_in => X1_signal2,
			F_in => Y1_signal2,
 			CLK  => CLK,
			A_out => Z0_signal3,
			B_out => P1_signal3,
			C_out => C1_signal3,
			D_out => X0_signal3,
			E_out => X1_signal3,
			F_out => Y1_signal3 );

	mult3 : celda_multiplicadora PORT MAP( 	
			Multiplicando => X0_signal3,
			Multiplicador => Y1_signal3,
			PP_IN => P1_signal3,
			C_IN => '0',
			C_OUT => C2_signal3,
			PP_OUT => Z1_signal3);

	pipe3 : pipem PORT MAP(
			A_in => Z0_signal3,
			B_in => C1_signal3,
			C_in => Z1_signal3,
			D_in => C2_signal3,
			E_in => X1_signal3,
			F_in => Y1_signal3,
 			CLK  => CLK,
			A_out => Z0_signal4,
			B_out => C1_signal4,
			C_out => Z1_signal4,
			D_out => C2_signal4,
			E_out => X1_signal4,
			F_out => Y1_signal4 );

	mult4 : celda_multiplicadora PORT MAP( 	
			Multiplicando => X1_signal4,
			Multiplicador => Y1_signal4,
			PP_IN => C1_signal4,
			C_IN => C2_signal4,
			C_OUT => Z3_signal4,
			PP_OUT => Z2_signal4);

	pipe4 : pipem PORT MAP(
			A_in => Z0_signal4,
			B_in => Z1_signal4,
			C_in => Z2_signal4,
			D_in => Z3_signal4,
			E_in => E_signal4,
			F_in => F_signal4,
			CLK  => CLK,
			A_out => Z0_signal5,
			B_out => Z1_signal5,
			C_out => Z2_signal5,
			D_out => Z3_signal5,
			E_out => E_signal5,
			F_out => F_signal5 );

	Z_o(0) <= Z0_signal5;
	Z_o(1) <= Z1_signal5;
	Z_o(2) <= Z2_signal5;
	Z_o(3) <= Z3_signal5;

END structural;


